[all-commits] [llvm/llvm-project] 715cf6: [RISCV] Add another isel optimization for (and (sh...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 715cf6ffb9a0491aa8749bf024d741de520fa1f2
      https://github.com/llvm/llvm-project/commit/715cf6ffb9a0491aa8749bf024d741de520fa1f2
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-24 (Fri, 24 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

  Log Message:
  -----------
  [RISCV] Add another isel optimization for (and (shl X, c2), c1).

Where c1 is a shifted mask with 32-c2 leading zeros and c3 trailing
zeros and c3>c2. We can select it as (slli (srliw X, c3-c2), c3).