[all-commits] [llvm/llvm-project] 638a41: [InstCombine] add tests for lshr-trunc-lshr; NFC

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  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 638a4147fc6400b928080c6d5656fbcee707a793
      https://github.com/llvm/llvm-project/commit/638a4147fc6400b928080c6d5656fbcee707a793
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-09-24 (Fri, 24 Sep 2021)

  Changed paths:
    M llvm/test/Transforms/InstCombine/lshr.ll

  Log Message:
  -----------
  [InstCombine] add tests for lshr-trunc-lshr; NFC


  Commit: 09e71c367af36a07cce04a812dcd9c62bebfbcdf
      https://github.com/llvm/llvm-project/commit/09e71c367af36a07cce04a812dcd9c62bebfbcdf
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2021-09-24 (Fri, 24 Sep 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/fcmp-logic.ll
    M llvm/test/CodeGen/X86/lzcnt-zext-cmp.ll

  Log Message:
  -----------
  [x86] convert logic-of-FP-compares to FP logic-of-vector-compares

This is motivated by the examples and discussion in:
https://llvm.org/PR51245
...and related bugs.

By using vector compares and vector logic, we can convert 2 'set'
instructions into 1 'movd' or 'movmsk' and generally improve
throughput/reduce instructions.

Unfortunately, we don't have a complete vector compare ISA before
AVX, so I left SSE-only out of this patch. Ie, we'd need extra logic
ops to simulate the missing predicates for SSE 'cmpp*', so it's not
as clearly a win.

Differential Revision: https://reviews.llvm.org/D110342


Compare: https://github.com/llvm/llvm-project/compare/1295694364d0...09e71c367af3