[all-commits] [llvm/llvm-project] 7d39a8: [RISCV] (1/2) Add the tail policy argument to buil...

Kai Wang via All-commits all-commits at lists.llvm.org
Fri Sep 24 02:10:58 PDT 2021 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7d39a8a92122e56b014e41606bf15623971d15ff
      https://github.com/llvm/llvm-project/commit/7d39a8a92122e56b014e41606bf15623971d15ff
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-09-24 (Fri, 24 Sep 2021)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll
    A llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

  Log Message:
  -----------
  [RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.

Add the tail policy argument to LLVM IR intrinsics. There are two policies for tail elements. Tail agnostic means users do not care about the values in the tail elements and tail undisturbed means the values in the tail elements need to be kept after the operation. In order to let users control the tail policy, we add an additional argument at the end of the argument list.

For unmasked operations, we have no maskedoff and the tail policy is always tail agnostic. If users want to keep tail elements under unmasked operations, they could use all one mask in the masked operations to do it. So, we only add the additional argument for masked operations for most cases. There are exceptions listed below.

In this patch, we do not handle the following cases to reduce the complexity of the patch. There could be two separate patches for them.

* Use dest argument to control tail policy
vmerge.vvm/vmerge.vxm/vmerge.vim (add _t builtins with additional dest argument)
vfmerge.vfm (add _t builtins with additional dest argument)
vmv.v.v (add _t builtins with additional dest argument)
vmv.v.x (add _t builtins with additional dest argument)
vmv.v.i (add _t builtins with additional dest argument)
vfmv.v.f (add _t builtins with additional dest argument)
vadc.vvm/vadc.vxm/vadc.vim (add _t builtins with additional dest argument)
vsbc.vvm/vsbc.vxm (add _t builtins with additional dest argument)

* Always has tail argument for masked/unmasked intrinsics
Vector Single-Width Integer Multiply-Add Instructions (add _t and _mt builtins)
Vector Widening Integer Multiply-Add Instructions (add _t and _mt builtins)
Vector Single-Width Floating-Point Fused Multiply-Add Instructions (add _t and _mt builtins)
Vector Widening Floating-Point Fused Multiply-Add Instructions (add _t and _mt builtins)
Vector Reduction Operations (add _t and _mt builtins)
Vector Slideup Instructions (add _t and _mt builtins)
Vector Slidedown Instructions (add _t and _mt builtins)

Discussion: https://github.com/riscv/rvv-intrinsic-doc/pull/101

Differential Revision: https://reviews.llvm.org/D105092


  Commit: 7afa61e71877a5b7892ffe4992f804cd84807240
      https://github.com/llvm/llvm-project/commit/7afa61e71877a5b7892ffe4992f804cd84807240
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-09-24 (Fri, 24 Sep 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfabs.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfneg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vneg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vadd-policy.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vand.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vasub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmax.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmin.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vneg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vor.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vrem.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsext.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsll.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsra.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vssra.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vssub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vwcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vxor.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vzext.c
    M clang/utils/TableGen/RISCVVEmitter.cpp

  Log Message:
  -----------
  [RISCV] (2/2) Add the tail policy argument to builtins/intrinsics.

Add the tail policy argument to Clang builtins. There
are two policies for tail elements. Tail agnostic means users do not
care about the values in the tail elements and tail undisturbed means
the values in the tail elements need to be kept after the operation. In
order to let users control the tail policy, we add an additional
argument at the end of the argument list.

For unmasked operations, we have no maskedoff and the tail policy is
always tail agnostic. If users want to keep tail elements under unmasked
operations, they could use all one mask in the masked operations to do
it. So, we only add the additional argument for masked operations for
most cases. There are exceptions listed below.

In this patch, we do not handle the following cases to reduce the
complexity of the patch. There could be two separate patches for them.

Use dest argument to control tail policy
vmerge.vvm/vmerge.vxm/vmerge.vim (add _t builtins with additional dest
argument)
vfmerge.vfm (add _t builtins with additional dest argument)
vmv.v.v (add _t builtins with additional dest argument)
vmv.v.x (add _t builtins with additional dest argument)
vmv.v.i (add _t builtins with additional dest argument)
vfmv.v.f (add _t builtins with additional dest argument)
vadc.vvm/vadc.vxm/vadc.vim (add _t builtins with additional dest
argument)
vsbc.vvm/vsbc.vxm (add _t builtins with additional dest argument)

Always has tail argument for masked/unmasked intrinsics
Vector Single-Width Integer Multiply-Add Instructions (add _t and _mt
builtins)
Vector Widening Integer Multiply-Add Instructions (add _t and _mt
builtins)
Vector Single-Width Floating-Point Fused Multiply-Add Instructions (add
_t and _mt builtins)
Vector Widening Floating-Point Fused Multiply-Add Instructions (add _t
and _mt builtins)
Vector Reduction Operations (add _t and _mt builtins)
Vector Slideup Instructions (add _t and _mt builtins)
Vector Slidedown Instructions (add _t and _mt builtins)

Discussion: https://github.com/riscv/rvv-intrinsic-doc/pull/101

Differential Revision: https://reviews.llvm.org/D109322


Compare: https://github.com/llvm/llvm-project/compare/dade83c02a11...7afa61e71877

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