[all-commits] [llvm/llvm-project] 40ddde: [TableGen] Allow targets to entirely ignore Psets ...

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 40ddde5d1fa7e5eadb76f6c3cc37dae2f80a8ca2
      https://github.com/llvm/llvm-project/commit/40ddde5d1fa7e5eadb76f6c3cc37dae2f80a8ca2
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2021-09-23 (Thu, 23 Sep 2021)

  Changed paths:
    A llvm/test/TableGen/bare-minimum-psets.td
    A llvm/test/TableGen/empty-psets.td
    M llvm/utils/TableGen/CodeGenRegisters.cpp

  Log Message:
  -----------
  [TableGen] Allow targets to entirely ignore Psets for registers

Tablegen currently expects targets to have at least one
pressure set for every broader register category. AMDGPU's
VGPR or AGPR, for instance, seemed to work correctly without
any pset, though we have forced one for each type to avoid
the assertion in computeRegUnitSets. However, psets can not
be entirely empty. At least one set is mandatory for every
target. This patch bypasses the assertion for the classes
when GeneratePressureSet is zero while ensuring the
RegUnitSets are not empty.

Reviewed By: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D110305