[all-commits] [llvm/llvm-project] 881122: [RISCV] Add more tests for (and (shl x, C2), C1) t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8811227a0c0ac398857988b4fce0fb4dc699468b
      https://github.com/llvm/llvm-project/commit/8811227a0c0ac398857988b4fce0fb4dc699468b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-23 (Thu, 23 Sep 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/shift-and.ll

  Log Message:
  -----------
  [RISCV] Add more tests for (and (shl x, C2), C1) that can be improved by using a pair of shifts. NFC

These tests have C1 as a shifted mask having no leading zeros and
C3 trailing zeros. If C3 is more than C2, we can select this as
(slli (srli x, C3-C2), C3).


  Commit: 70f50114f37e86bd4869a75b1a8313440bd55780
      https://github.com/llvm/llvm-project/commit/70f50114f37e86bd4869a75b1a8313440bd55780
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-23 (Thu, 23 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/shift-and.ll

  Log Message:
  -----------
  [RISCV] Add another isel optimization for (and (shl x, c2), c1)

Turn (and (shl x, c2), c1) -> (slli (srli x, c3-c2), c3) if c1 is a
shifted mask with no leading zeros and c3 trailing zeros where c3
is greater than c2.


Compare: https://github.com/llvm/llvm-project/compare/093245ed9ee4...70f50114f37e