[all-commits] [llvm/llvm-project] 19734a: [RISCV] Add more tests for (and (srl x, C2), C1) t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 19734ae6f05498a75d4bb3960be06f5d704f8528
      https://github.com/llvm/llvm-project/commit/19734ae6f05498a75d4bb3960be06f5d704f8528
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-23 (Thu, 23 Sep 2021)

  Changed paths:
    A llvm/test/CodeGen/RISCV/shift-and.ll

  Log Message:
  -----------
  [RISCV] Add more tests for (and (srl x, C2), C1) that can be improved by using a pair of shifts. NFC

These tests have C1 as a shifted mask having C2 leading zeros and some
number of trailing zeros, C3. We can select this as
(slli (srli x, C2+C3), C3) or (slli (srliw x, C2+C3), C3).


  Commit: 4a69551d663e42453c3ad5ab799326fe2ddc9657
      https://github.com/llvm/llvm-project/commit/4a69551d663e42453c3ad5ab799326fe2ddc9657
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-23 (Thu, 23 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/shift-and.ll

  Log Message:
  -----------
  [RISCV] Add more isel optimizations for (and (shr x, c2), c1).

Turn (and (shr x, c2), c1) -> (slli (srli x, c2+c3), c3) if c1 is a
shifted mask with c2 leading zeros and c3 trailing zeros.

When the leading zeros is C2+32 we can use SRLIW in place of SRLI.


Compare: https://github.com/llvm/llvm-project/compare/5188e2c9ce1f...4a69551d663e