[all-commits] [llvm/llvm-project] ebc5fe: [RISCV] Update mir tests.

[Kai Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ebc5feb4ed6b1f59a000669030f9639bf1763403
      https://github.com/llvm/llvm-project/commit/ebc5feb4ed6b1f59a000669030f9639bf1763403
  Author: Hsiangkai Wang <kai.wang at sifive.com>
  Date:   2021-09-23 (Thu, 23 Sep 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
    M llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
    M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
    M llvm/test/CodeGen/RISCV/rvv/get-vlen-debugloc.mir
    M llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir
    M llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir
    M llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-copy.mir
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  [RISCV] Update mir tests.