[all-commits] [llvm/llvm-project] ca999f: [OpenMP][Offloading] Use bitset to indicate execut...

[Shilei Tian via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ca999f719117f916b333a794cc8c59984ae40dd2
      https://github.com/llvm/llvm-project/commit/ca999f719117f916b333a794cc8c59984ae40dd2
  Author: Shilei Tian <tianshilei1992 at gmail.com>
  Date:   2021-09-22 (Wed, 22 Sep 2021)

  Changed paths:
    M clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
    M clang/test/OpenMP/nvptx_target_parallel_proc_bind_codegen.cpp
    M clang/test/OpenMP/nvptx_target_parallel_reduction_codegen.cpp
    M clang/test/OpenMP/nvptx_target_simd_codegen.cpp
    M clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp
    M llvm/include/llvm/Frontend/OpenMP/OMPConstants.h
    M llvm/lib/Transforms/IPO/OpenMPOpt.cpp
    M llvm/test/Transforms/OpenMP/get_hardware_num_threads_in_block_fold.ll
    M llvm/test/Transforms/OpenMP/is_spmd_exec_mode_fold.ll
    M llvm/test/Transforms/OpenMP/spmdization.ll
    M llvm/test/Transforms/OpenMP/spmdization_assumes.ll
    M llvm/test/Transforms/OpenMP/spmdization_guarding.ll
    M openmp/libomptarget/plugins/cuda/CMakeLists.txt
    M openmp/libomptarget/plugins/cuda/src/rtl.cpp

  Log Message:
  -----------
  [OpenMP][Offloading] Use bitset to indicate execution mode instead of value

The execution mode of a kernel is stored in a global variable, whose value means:
- 0 - SPMD mode
- 1 - indicates generic mode
- 2 - SPMD mode execution with generic mode semantics

We are going to add support for SIMD execution mode. It will be come with another
execution mode, such as SIMD-generic mode. As a result, this value-based indicator
is not flexible.

This patch changes to bitset based solution to encode execution mode. Each
position is:
[0] - generic mode
[1] - SPMD mode
[2] - SIMD mode (will be added later)

In this way, `0x1` is generic mode, `0x2` is SPMD mode, and `0x3` is SPMD mode
execution with generic mode semantics. In the future after we add the support for
SIMD mode, `0b1xx` will be in SIMD mode.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D110029