[all-commits] [llvm/llvm-project] 3a00e5: AArch64: use indivisible cmpxchg for 128-bit atomi...

[Tim Northover via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3a00e58c2fca0c20d3792c897ef1ea54b6a168a0
      https://github.com/llvm/llvm-project/commit/3a00e58c2fca0c20d3792c897ef1ea54b6a168a0
  Author: Tim Northover <t.p.northover at gmail.com>
  Date:   2021-09-22 (Wed, 22 Sep 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll

  Log Message:
  -----------
  AArch64: use indivisible cmpxchg for 128-bit atomic loads at O0

Like normal atomicrmw operations, at -O0 the simple register-allocator can
insert spills into the LL/SC loop if it's expanded and visible when regalloc
runs. This can cause the operation to never succeed by repeatedly clearing the
monitor. Instead expand to a cmpxchg, which has a pseudo-instruction for -O0.