[all-commits] [llvm/llvm-project] d5681f: [SelectionDAG] Add PromoteIntOp_INSERT_SUBVECTOR.

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d5681f1d688a45c000dd1e2c4f4d3678e0440b94
      https://github.com/llvm/llvm-project/commit/d5681f1d688a45c000dd1e2c4f4d3678e0440b94
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2021-09-22 (Wed, 22 Sep 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll

  Log Message:
  -----------
  [SelectionDAG] Add PromoteIntOp_INSERT_SUBVECTOR.

This is required to codegen something like:
  <vscale x 8 x i16> @llvm.experimental.vector.insert(<vscale x 8 x i16> %vec,
                                                      <vscale x 2 x i16> %subvec,
                                                      i64 %idx)
where the output vector is legal, but the input vector needs promoting.

It implements this by performing the whole operation on the promoted type,
and then truncating the result.

Reviewed By: david-arm, craig.topper

Differential Revision: https://reviews.llvm.org/D110059