[all-commits] [llvm/llvm-project] 02cd8a: [ARM] Allow smaller VMOVL in tail predicated loops

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02cd8a6b915a9dab32fdd91167f875ce5f67ebd4
      https://github.com/llvm/llvm-project/commit/02cd8a6b915a9dab32fdd91167f875ce5f67ebd4
  Author: David Green <david.green at arm.com>
  Date:   2021-09-22 (Wed, 22 Sep 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrFormats.td
    M llvm/lib/Target/ARM/ARMInstrMVE.td
    M llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
    M llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
    M llvm/test/CodeGen/Thumb2/mve-vmovlloop.ll
    M llvm/unittests/Target/ARM/MachineInstrTest.cpp

  Log Message:
  -----------
  [ARM] Allow smaller VMOVL in tail predicated loops

This allows VMOVL in tail predicated loops so long as the the vector
size the VMOVL is extending into is less than or equal to the size of
the VCTP in the tail predicated loop. These cases represent a
sign-extend-inreg (or zero-extend-inreg), which needn't block tail
predication as in https://godbolt.org/z/hdTsEbx8Y.

For this a vecsize has been added to the TSFlag bits of MVE
instructions, which stores the size of the elements that the MVE
instruction operates on. In the case of multiple size (such as a
MVE_VMOVLs8bh that extends from i8 to i16, the largest size was be
chosen). The sizes are encoded as 00 = i8, 01 = i16, 10 = i32 and 11 =
i64, which often (but not always) comes from the instruction encoding
directly. A unit test was added, and although only a subset of the
vecsizes are currently used, the rest should be useful for other cases.

Differential Revision: https://reviews.llvm.org/D109706