[all-commits] [llvm/llvm-project] 1a3329: [AMDGPU] Filtering out the inactive lanes bits whe...

[alex-t via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a33294652b24eff17a1f222f1f11f4986cdce5a
      https://github.com/llvm/llvm-project/commit/1a33294652b24eff17a1f222f1f11f4986cdce5a
  Author: alex-t <alexander.timofeev at amd.com>
  Date:   2021-09-21 (Tue, 21 Sep 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    A llvm/test/CodeGen/AMDGPU/copy_to_scc.ll

  Log Message:
  -----------
  [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC

Normally, given that the DA results are kept consistent over the selection DAG, uniform comparisons get selected to S_CMP_* but divergent to V_CMP_*.  Sometimes, for the sake of efficiency,  SSA subgraphs may be converted to VALU to avoid repeatedly copying data back and forth. Hence we have to be able to sustain the correctness passing the i1 from VALU to SALU context and vice versa.

VALU operations only process the active lanes of the VGPR and ignore inactive ones.
Active lanes correspond to 1 bit in the EXEC mask register.
SALU represents i1 as just one bit but VALU as 64bits: 0/1 and 0/(0xffffffffffffffff & EXEC) respectively.
SALU uses one-bit conditional flag SCC but VALU - VCC that is a pair of 32-bit SGPRs

To expose SCC to the VALU context we need to convert the one-bit boolean value to the appropriate 64bit.
To return back to the SALU context we need to do the opposite.

To correctly convert 64bit VALU boolean to either 0 or 1 we need to filter out the bits corresponding to the inactive lanes.

Reviewed By: piotr

Differential Revision: https://reviews.llvm.org/D109900