[all-commits] [llvm/llvm-project] f417d9: [InstCombine] Eliminate vector reverse if all inpu...

[Usman Nadeem via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f417d9d821118ef330b263c4c7ad9d3cda30f406
      https://github.com/llvm/llvm-project/commit/f417d9d821118ef330b263c4c7ad9d3cda30f406
  Author: Usman Nadeem <mnadeem at quicinc.com>
  Date:   2021-09-20 (Mon, 20 Sep 2021)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
    A llvm/test/Transforms/InstCombine/vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll

  Log Message:
  -----------
  [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses

Differential Revision: https://reviews.llvm.org/D109808

Change-Id: I1a10d2bc33acbe0ea353c6cb3d077851391fe73e