[all-commits] [llvm/llvm-project] 73e5b9: [RISCV] Select (srl (sext_inreg X, i32), uimm5) to...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 73e5b9ea90ba857dd7f0f6b79dc39dfc90ad66ea
      https://github.com/llvm/llvm-project/commit/73e5b9ea90ba857dd7f0f6b79dc39dfc90ad66ea
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-16 (Thu, 16 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
    M llvm/test/CodeGen/RISCV/srem-lkk.ll

  Log Message:
  -----------
  [RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.

SimplifyDemandedBits can turn srl into sra if the bits being shifted
in aren't demanded. This patch can recover the original sra in some cases.

I've renamed the tablegen class for detecting W users since the "overflowing operator"
term I originally borrowed from Operator.h does not include srl.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D109162