[all-commits] [llvm/llvm-project] 4a36e9: RegAllocGreedy: Account for reserved registers in ...

Tue Sep 14 18:00:52 PDT 2021

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4a36e96c3fc2a9128097bfc4f907ccebc5dc66af
      https://github.com/llvm/llvm-project/commit/4a36e96c3fc2a9128097bfc4f907ccebc5dc66af
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
    M llvm/test/CodeGen/AMDGPU/frem.ll
    A llvm/test/CodeGen/AMDGPU/greedy-global-heuristic.mir
    M llvm/test/CodeGen/AMDGPU/half.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/srl.ll
    M llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/ARM/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/ARM/umulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/Hexagon/reg-scavengebug-2.ll
    M llvm/test/CodeGen/Mips/cconv/vector.ll
    M llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
    M llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/rv32zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/stack-store-check.ll
    M llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
    M llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
    M llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
    M llvm/test/CodeGen/Thumb2/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
    M llvm/test/CodeGen/X86/2008-04-16-ReMatBug.ll
    M llvm/test/CodeGen/X86/64-bit-shift-by-32-minus-y.ll
    M llvm/test/CodeGen/X86/abs.ll
    M llvm/test/CodeGen/X86/avx512-calling-conv.ll
    M llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
    M llvm/test/CodeGen/X86/avx512-select.ll
    M llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/bitreverse.ll
    M llvm/test/CodeGen/X86/bool-vector.ll
    M llvm/test/CodeGen/X86/bswap.ll
    M llvm/test/CodeGen/X86/build-vector-128.ll
    M llvm/test/CodeGen/X86/clear-highbits.ll
    M llvm/test/CodeGen/X86/combine-sbb.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
    M llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
    M llvm/test/CodeGen/X86/fp128-cast.ll
    M llvm/test/CodeGen/X86/fptosi-sat-scalar.ll
    M llvm/test/CodeGen/X86/fshr.ll
    M llvm/test/CodeGen/X86/funnel-shift-rot.ll
    M llvm/test/CodeGen/X86/funnel-shift.ll
    M llvm/test/CodeGen/X86/gather-addresses.ll
    M llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
    M llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
    M llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
    M llvm/test/CodeGen/X86/i128-mul.ll
    M llvm/test/CodeGen/X86/i128-sdiv.ll
    M llvm/test/CodeGen/X86/i256-add.ll
    M llvm/test/CodeGen/X86/i64-to-float.ll
    M llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
    M llvm/test/CodeGen/X86/known-signbits-vector.ll
    M llvm/test/CodeGen/X86/legalize-shl-vec.ll
    M llvm/test/CodeGen/X86/load-combine.ll
    M llvm/test/CodeGen/X86/masked_gather_scatter.ll
    M llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
    M llvm/test/CodeGen/X86/merge-consecutive-stores-nt.ll
    M llvm/test/CodeGen/X86/mmx-arith.ll
    M llvm/test/CodeGen/X86/mul-constant-i64.ll
    M llvm/test/CodeGen/X86/mul-constant-result.ll
    M llvm/test/CodeGen/X86/mul-i1024.ll
    M llvm/test/CodeGen/X86/mul-i256.ll
    M llvm/test/CodeGen/X86/mul-i512.ll
    M llvm/test/CodeGen/X86/mul128.ll
    M llvm/test/CodeGen/X86/neg-abs.ll
    M llvm/test/CodeGen/X86/nontemporal.ll
    M llvm/test/CodeGen/X86/nosse-vector.ll
    M llvm/test/CodeGen/X86/overflow.ll
    M llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll
    M llvm/test/CodeGen/X86/popcnt.ll
    M llvm/test/CodeGen/X86/pr31088.ll
    M llvm/test/CodeGen/X86/pr32284.ll
    M llvm/test/CodeGen/X86/pr32329.ll
    M llvm/test/CodeGen/X86/pr32610.ll
    M llvm/test/CodeGen/X86/pr34080-2.ll
    M llvm/test/CodeGen/X86/pr46527.ll
    M llvm/test/CodeGen/X86/sadd_sat.ll
    M llvm/test/CodeGen/X86/scheduler-backtracking.ll
    M llvm/test/CodeGen/X86/sdiv_fix.ll
    M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
    M llvm/test/CodeGen/X86/select.ll
    M llvm/test/CodeGen/X86/setcc-wide-types.ll
    M llvm/test/CodeGen/X86/shrink_vmul.ll
    M llvm/test/CodeGen/X86/smax.ll
    M llvm/test/CodeGen/X86/smin.ll
    M llvm/test/CodeGen/X86/smul_fix.ll
    M llvm/test/CodeGen/X86/smul_fix_sat.ll
    M llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
    M llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
    M llvm/test/CodeGen/X86/sshl_sat.ll
    M llvm/test/CodeGen/X86/sshl_sat_vec.ll
    M llvm/test/CodeGen/X86/stack-align-memcpy.ll
    M llvm/test/CodeGen/X86/statepoint-vreg-unlimited-tied-opnds.ll
    M llvm/test/CodeGen/X86/subvector-broadcast.ll
    M llvm/test/CodeGen/X86/uadd_sat.ll
    M llvm/test/CodeGen/X86/udiv_fix_sat.ll
    M llvm/test/CodeGen/X86/umax.ll
    M llvm/test/CodeGen/X86/umin.ll
    M llvm/test/CodeGen/X86/umul-with-overflow.ll
    M llvm/test/CodeGen/X86/umul_fix.ll
    M llvm/test/CodeGen/X86/umul_fix_sat.ll
    M llvm/test/CodeGen/X86/umulo-64-legalisation-lowering.ll
    M llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll
    M llvm/test/CodeGen/X86/ushl_sat.ll
    M llvm/test/CodeGen/X86/ushl_sat_vec.ll
    M llvm/test/CodeGen/X86/usub_sat.ll
    M llvm/test/CodeGen/X86/vec-strict-cmp-128.ll
    M llvm/test/CodeGen/X86/vec-strict-cmp-sub128.ll
    M llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
    M llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll
    M llvm/test/CodeGen/X86/vec_shift4.ll
    M llvm/test/CodeGen/X86/vec_umulo.ll
    M llvm/test/CodeGen/X86/vector-fshl-128.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
    M llvm/test/CodeGen/X86/vector-gep.ll
    M llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
    M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
    M llvm/test/CodeGen/X86/vector-rotate-128.ll
    M llvm/test/CodeGen/X86/vector-sext.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
    M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
    M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
    M llvm/test/CodeGen/X86/vshift-6.ll
    M llvm/test/CodeGen/X86/widen_cast-4.ll
    M llvm/test/CodeGen/X86/xmulo.ll

  Log Message:
  -----------
  RegAllocGreedy: Account for reserved registers in num regs heuristic

This simple heuristic uses the estimated live range length combined
with the number of registers in the class to switch which heuristic to
use. This was taking the raw number of registers in the class, even
though not all of them may be available. AMDGPU heavily relies on
dynamically reserved numbers of registers based on user attributes to
satisfy occupancy constraints, so the raw number is highly misleading.

There are still a few problems here. In the original testcase that
made me notice this, the live range size is incorrect after the
scheduler rearranges instructions, since the instructions don't have
the original InstrDist offsets. Additionally, I think it would be more
appropriate to use the number of disjointly allocatable registers in
the class. For the AMDGPU register tuples, there are a large number of
registers in each tuple class, but only a small fraction can actually
be allocated at the same time since they all overlap with each
other. It seems we do not have a query that corresponds to the number
of independently allocatable registers. Relatedly, I'm still debugging
some allocation failures where overlapping tuples seem to not be
handled correctly.

The test changes are mostly noise. There are a handful of x86 tests
that look like regressions with an additional spill, and a handful
that now avoid a spill. The worst looking regression is likely
test/Thumb2/mve-vld4.ll which introduces a few additional
spills. test/CodeGen/AMDGPU/soft-clause-exceeds-register-budget.ll
shows a massive improvement by completely eliminating a large number
of spills inside a loop.