[all-commits] [llvm/llvm-project] 5041a4: [PowerPC] Exploit Prefixed Load/Stores using the r...

[Amy Kwan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5041a485b948e55e54338779f2248c45402b0ae7
      https://github.com/llvm/llvm-project/commit/5041a485b948e55e54338779f2248c45402b0ae7
  Author: Amy Kwan <amy.kwan1 at ibm.com>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/lib/Target/PowerPC/PPCInstrPrefix.td
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll
    M llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll
    M llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll
    M llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll
    M llvm/test/CodeGen/PowerPC/f128_ldst.ll
    M llvm/test/CodeGen/PowerPC/int128_ldst.ll
    M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
    M llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
    A llvm/test/CodeGen/PowerPC/p10-fi-elim.ll
    M llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/pcrel_ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-double-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-float-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-i16-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-i32-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-i64-ldst.ll
    M llvm/test/CodeGen/PowerPC/scalar-i8-ldst.ll
    M llvm/test/CodeGen/PowerPC/vec_insert_elt.ll
    M llvm/test/CodeGen/PowerPC/vector-ldst.ll

  Log Message:
  -----------
  [PowerPC] Exploit Prefixed Load/Stores using the refactored Load/Store Implementation

This patch exploits the prefixed load and store instructions utilizing the
refactored load/store implementation introduced in D93370.

Prefixed load and store instructions are emitted whenever we are loading or
storing a value with an offset that fits into a 34-bit signed immediate.
Patterns for the prefixed load and stores are added in this patch, as well as
the implementation that detects when we are loading and storing a value with an
offset that fits in 34-bits.

Differential Revision: https://reviews.llvm.org/D96075