[all-commits] [llvm/llvm-project] 5a6dfb: [ARM] Teach DemandedVectorElts about VMOVN lanes

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5a6dfbb8cd26376120e16ceae650f6c9b7a00950
      https://github.com/llvm/llvm-project/commit/5a6dfbb8cd26376120e16ceae650f6c9b7a00950
  Author: David Green <david.green at arm.com>
  Date:   2021-09-14 (Tue, 14 Sep 2021)

  Changed paths:
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
    M llvm/lib/Target/ARM/ARMTargetTransformInfo.h
    M llvm/test/Transforms/InstCombine/ARM/mve-narrow.ll

  Log Message:
  -----------
  [ARM] Teach DemandedVectorElts about VMOVN lanes

The class of instructions that write to narrow top/bottom lanes only
demand the even or odd elements of the input lanes. Which means that a
pair of VMOVNT; VMOVNB demands no lanes from the original input. This
teaches that to instcombine from the target hooks available through
ARMTTIImpl.

Differential Revision: https://reviews.llvm.org/D109325