[all-commits] [llvm/llvm-project] 915e9e: [llvm][sve] Lowering for VLS masked extending loads

[David Truby via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 915e9e76bf9ac4ec57db83fe4e1d20a7c230ad3d
      https://github.com/llvm/llvm-project/commit/915e9e76bf9ac4ec57db83fe4e1d20a7c230ad3d
  Author: David Truby <david.truby at arm.com>
  Date:   2021-09-13 (Mon, 13 Sep 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll

  Log Message:
  -----------
  [llvm][sve] Lowering for VLS masked extending loads

This extends the custom lowering for extending loads on
fixed length vectors in SVE to support masked extending loads.

The existing tests for correct behaviour of masked extending loads
exhibit bad code generation due to the legalistaion of i1 vectors.
They have been left as-is and new tests have been added that do not
exhibit this behaviour.

Differential Revision: https://reviews.llvm.org/D108200