[all-commits] [llvm/llvm-project] 283879: [RISCV] Initial support .insn directive for the as...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 283879793dc787225992496587581ec77b6b0610
      https://github.com/llvm/llvm-project/commit/283879793dc787225992496587581ec77b6b0610
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-12 (Sun, 12 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    A llvm/test/MC/RISCV/insn-invalid.s
    A llvm/test/MC/RISCV/insn.s

  Log Message:
  -----------
  [RISCV] Initial support .insn directive for the assembler.

This allows for a custom encoding to be emitted. It can also be
used with inline assembly to allow the custom instruction to be
register allocated like other instructions.

I initially started from SystemZ's implementation, but some of
the formats allow operands to be specified in multiple ways so I
had to add support for matching different operand class lists for
the same format. That implementation is a simplified version of
what is emitted by tablegen for regular instructions.

I've left out the compressed formats. And I haven't supported the
named opcodes like LUI or OP_IMM_32. Those can be added in future
patches.

Documentation can be found here https://sourceware.org/binutils/docs-2.37/as/RISC_002dV_002dFormats.html

Reviewed By: jrtc27, MaskRay

Differential Revision: https://reviews.llvm.org/D108602