[all-commits] [llvm/llvm-project] ea7b2c: [Test][AggressiveInstCombine] Add test for `udiv` ...

[Anton Afanasyev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ea7b2c147fefece043f35d150652d50357250e96
      https://github.com/llvm/llvm-project/commit/ea7b2c147fefece043f35d150652d50357250e96
  Author: Anton Afanasyev <anton.a.afanasyev at gmail.com>
  Date:   2021-09-10 (Fri, 10 Sep 2021)

  Changed paths:
    A llvm/test/Transforms/AggressiveInstCombine/trunc_udivrem.ll

  Log Message:
  -----------
  [Test][AggressiveInstCombine] Add test for `udiv` and `urem`

Precommit test for D109515


  Commit: 54d8ebbbfdb348a6d0354fe7909d9ab146dada5b
      https://github.com/llvm/llvm-project/commit/54d8ebbbfdb348a6d0354fe7909d9ab146dada5b
  Author: Anton Afanasyev <anton.a.afanasyev at gmail.com>
  Date:   2021-09-10 (Fri, 10 Sep 2021)

  Changed paths:
    M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
    M llvm/test/Transforms/AggressiveInstCombine/trunc_udivrem.ll

  Log Message:
  -----------
  [AggressiveInstCombine] Add `udiv` and `urem` instrs to TruncInstCombine DAG

Add `udiv` and `urem` instructions to the DAG post-dominated by `trunc`,
allowing TruncInstCombine to reduce bitwidth of expressions containing these
instructions. It is sufficient to require that all truncated bits of both
operands are zeros: https://alive2.llvm.org/ce/z/yiithn
(`urem` case is identical).

Differential Revision: https://reviews.llvm.org/D109515


Compare: https://github.com/llvm/llvm-project/compare/d2f206e0afeb...54d8ebbbfdb3