[all-commits] [llvm/llvm-project] 4bc8db: [RISCV] Add SiFive cores E and S series

[Alexander Pivovarov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6
      https://github.com/llvm/llvm-project/commit/4bc8dbe0cae32f15008c1e98e7dd7d128e9dcbb6
  Author: Alexander Pivovarov <apivovarov at gmail.com>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/include/llvm/Support/RISCVTargetParser.def
    M llvm/lib/Target/RISCV/RISCV.td

  Log Message:
  -----------
  [RISCV] Add SiFive cores E and S series

Add SiFive cores E20, E21, E24, E34, S21, S54 and S76

Differential Revision: https://reviews.llvm.org/D109260