[all-commits] [llvm/llvm-project] b04c09: [RISCV] Use V0 instead of VMV0: for mask vectors i...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b04c09c07cfa073984b94dc1c8041201f43274d4
      https://github.com/llvm/llvm-project/commit/b04c09c07cfa073984b94dc1c8041201f43274d4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    M llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll

  Log Message:
  -----------
  [RISCV] Use V0 instead of VMV0: for mask vectors in isel patterns.

This is consistent with the RVV intrinsic patterns. This has been
shown to prevent some "ran out of registers" errors in our internal
testing.

Unfortunately, there are some regressions on LMUL=8 tests in here.
I think the lack of registers with LMUL=8 just makes it very hard
to schedule correctly.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D109245