[all-commits] [llvm/llvm-project] 1f1619: [RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1f161919065fbfa2b39b8f373553a64b89f826f8
      https://github.com/llvm/llvm-project/commit/1f161919065fbfa2b39b8f373553a64b89f826f8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-08 (Wed, 08 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir

  Log Message:
  -----------
  [RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos

The expansion of these pseudos creates ADD instructions. Those
ADDs modify a GPR so that it is no longer contains the same value
as the input base pointer. Therefore, I believe we should have a
GPR as a Def on these instructions and expansion should get the
destination register for the ADDs from that operand.

At least in our tests here this works out so that register
scavenging picks the same register as the base pointer.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D109405