[all-commits] [llvm/llvm-project] 7023ce: [AArch64][Global ISel] Add sext/zext of vector ext...

[Irina Dobrescu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7023cefe61913fefd82eb7ee463a2c8d01faf1ae
      https://github.com/llvm/llvm-project/commit/7023cefe61913fefd82eb7ee463a2c8d01faf1ae
  Author: Irina Dobrescu <irina.dobrescu at arm.com>
  Date:   2021-09-07 (Tue, 07 Sep 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    A llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir
    A llvm/test/CodeGen/AArch64/extract-sext-zext.ll

  Log Message:
  -----------
  [AArch64][Global ISel] Add sext/zext of vector extract improvements

This patch adds improvements for sext/zext of a vector extract in Global
ISel.

For example, this piece of code:

define i64 @si64(<4 x i32> %0, i32 %1) {
  %3 = extractelement <4 x i32> %0, i64 1
  %s = sext i32 %3 to i64
  ret i64 %s
}

Used to have this lowering:
si64:
  mov s0, v0.s[1]
  fmov w8, s0
  sxtw x0, w8
  ret

Whereas this patch makes it lower to this:
si64:
  smov x0, v0.h[0]
  ret

Differential Revision: https://reviews.llvm.org/D108137