[all-commits] [llvm/llvm-project] 1dcd90: [AArch64][ISel] NFC: DAG.getMachineFunction() -> MF

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1dcd900d1d852cb26d153989d02de944ce1f3b43
      https://github.com/llvm/llvm-project/commit/1dcd900d1d852cb26d153989d02de944ce1f3b43
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2021-09-03 (Fri, 03 Sep 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  Log Message:
  -----------
  [AArch64][ISel] NFC: DAG.getMachineFunction() -> MF

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D109135


  Commit: dc5dd77ac70089067236cf8071add95f153d5eba
      https://github.com/llvm/llvm-project/commit/dc5dd77ac70089067236cf8071add95f153d5eba
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2021-09-03 (Fri, 03 Sep 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
    M llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
    M llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s
    M llvm/test/MC/AArch64/SME/streaming-mode-neon.s

  Log Message:
  -----------
  [AArch64][SME] Support NEON vector to GPR integer moves in streaming mode

A small subset of the NEON instruction set is legal in streaming mode.
This patch adds support for the following vector to integer move
instructions:

  0x00 1110 0000 0001 0010 11xx xxxx xxxx # SMOV W|Xd,Vn.B[0]
  0x00 1110 0000 0010 0010 11xx xxxx xxxx # SMOV W|Xd,Vn.H[0]
  0100 1110 0000 0100 0010 11xx xxxx xxxx # SMOV Xd,Vn.S[0]
  0000 1110 0000 0001 0011 11xx xxxx xxxx # UMOV Wd,Vn.B[0]
  0000 1110 0000 0010 0011 11xx xxxx xxxx # UMOV Wd,Vn.H[0]
  0000 1110 0000 0100 0011 11xx xxxx xxxx # UMOV Wd,Vn.S[0]
  0100 1110 0000 1000 0011 11xx xxxx xxxx # UMOV Xd,Vn.D[0]

Only the zero index variants are legal, all others indexes are illegal.
To support this, new instructions are defined specifically for zero
index which is hardcoded, along an implicit 'VectorIndex0' operand.
Since the index operand is implicit and takes no bits in the encoding,
custom decoding is required to add the operand.

I'm not sure if this is the best approach but the predicate constraint
on a subset of an operand is unusual. Would be interested to hear some
alternatives.

The instructions are predicated on 'HasNEONorStreamingSVE', i.e. they're
enabled by either +neon or +streaming-sve. This follows on from the work
in D106272 to support the subset of SVE(2) instructions that are legal
in streaming mode.

Depends on D107902.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D107903


Compare: https://github.com/llvm/llvm-project/compare/0c375296cc77...dc5dd77ac700