[all-commits] [llvm/llvm-project] 6cd4b5: [RISCV] Add SiFive core S51

[Alexander Pivovarov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6cd4b508a8a51ecd16d2b0297dfeb445ab41b42e
      https://github.com/llvm/llvm-project/commit/6cd4b508a8a51ecd16d2b0297dfeb445ab41b42e
  Author: Alexander Pivovarov <apivovarov at gmail.com>
  Date:   2021-09-02 (Thu, 02 Sep 2021)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/include/llvm/Support/RISCVTargetParser.def
    M llvm/lib/Target/RISCV/RISCV.td

  Log Message:
  -----------
  [RISCV] Add SiFive core S51

Add SiFive core s51 as rv64imac RocketModel

Reviewed-By: MaskRay, evandro
Differential Revision: https://reviews.llvm.org/D108886