[all-commits] [llvm/llvm-project] b5fd6b: [RISCV] Teach instruction selection to elide sext....

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b5fd6b46f59e2bf0807621814ba9bef6645eec58
      https://github.com/llvm/llvm-project/commit/b5fd6b46f59e2bf0807621814ba9bef6645eec58
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-09-02 (Thu, 02 Sep 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Teach instruction selection to elide sext.w in some cases.

If a sext_inreg is up for isel, and all its users are W instructions,
we can skip emitting the sext_inreg. This helpful if the producing
instruction can't become a W instruction.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D108966