[all-commits] [llvm/llvm-project] f57531: [Codegen][TLI][X86] SimplifyMultipleUseDemandedBit...

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f5753125f03ac3e2876069420496d4920cf26749
      https://github.com/llvm/llvm-project/commit/f5753125f03ac3e2876069420496d4920cf26749
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2021-09-02 (Thu, 02 Sep 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
    M llvm/test/CodeGen/X86/avg.ll
    M llvm/test/CodeGen/X86/horizontal-sum.ll

  Log Message:
  -----------
  [Codegen][TLI][X86] SimplifyMultipleUseDemandedBits(): 0'th vec subreg widening is free, try to perform it earlier

I believe, the profitability reasoning here is correct
"sub"reg is already located within the 0'th subreg of wider reg,
so if we have suvector insertion at index 0 into undef,
then it's always free do to.

After this, D109065 finally avoids the regression in D108382.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D109074