[all-commits] [llvm/llvm-project] 4dab15: [AMDGPU] Introduce RC flags for vector register cl...
Christudasan Devadasan via All-commits
all-commits at lists.llvm.org
Wed Sep 1 00:04:01 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 4dab15288d69c9002c98473588232d6ecbd7d29e
https://github.com/llvm/llvm-project/commit/4dab15288d69c9002c98473588232d6ecbd7d29e
Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
Date: 2021-09-01 (Wed, 01 Sep 2021)
Changed paths:
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
[AMDGPU] Introduce RC flags for vector register classes
Configure and use the TSFlags in TargetRegisterClass to
have unique flags for VGPR and AGPR register classes.
The vector register class queries like `hasVGPRs` will
now become more efficient with just a bitwise operation.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D108815
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