[all-commits] [llvm/llvm-project] 6a7504: [TableGen] Allow target specific flags for Registe...

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a75041a1614af1ca787af5a18ea9ddbe4dd5c16
      https://github.com/llvm/llvm-project/commit/6a75041a1614af1ca787af5a18ea9ddbe4dd5c16
  Author: Christudasan Devadasan <Christudasan.Devadasan at amd.com>
  Date:   2021-08-31 (Tue, 31 Aug 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/include/llvm/Target/Target.td
    A llvm/test/TableGen/RegisterInfoEmitter-tsflags.td
    M llvm/utils/TableGen/CodeGenRegisters.cpp
    M llvm/utils/TableGen/CodeGenRegisters.h
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen] Allow target specific flags for RegisterClass

Analogous to the TSFlags for machine instructions, this
patch introduces a bit vector for register classes to have
target specific flags that become a tablegened value in
TargetRegisterClass.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D108767