[all-commits] [llvm/llvm-project] 9e2d14: [X86] Copy X86SchedSkylakeServer.td to X86SchedIce...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9e2d14c2851269928df28a38c76d4d87536bcd49
      https://github.com/llvm/llvm-project/commit/9e2d14c2851269928df28a38c76d4d87536bcd49
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-08-31 (Tue, 31 Aug 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86PfmCounters.td
    A llvm/lib/Target/X86/X86SchedIceLake.td

  Log Message:
  -----------
  [X86] Copy X86SchedSkylakeServer.td to X86SchedIceLake.td

Icelake, Rocketlake and Tigerlake targets currently use the SkylakeServer scheduler model, despite being a later microarchitecture, leading to both reported bugs (PR48110) and discrepancies when comparing llvm-mca reports to other profiling tools (OSACA, uops, uica, etc.). And tbh I'm getting sick of llvm-mca getting blamed for what are backend scheduler model issues :-(

This patch doesn't attempt to fix any of these discrepancies - there should be no changes in codegen - its a setup patch that copies the skx model, renames all the resources, adds the additional ports (but doesn't reference them yet) and updates the llvm-exegesis pfm counter mappings (based off https://sourceforge.net/p/perfmon2/libpfm4/ci/master/tree/lib/events/intel_icl_events.h).

This should make it trivial for anyone with hardware access to use llvm-exegesis reports to iteratively improve the model (my attempts to get hold of a cheap tiger lake box haven't been fruitful yet....).

I will copy the SkylakeServer llvm-mca resource tests as follow up commits - the diff should entirely be the resource renames.

Differential Revision: https://reviews.llvm.org/D108914