[all-commits] [llvm/llvm-project] 3f919d: [AArch64][SVE] Use getPTrue uniformly.NFC.

[junparser via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3f919dfe0de84b9ec288d6126eb8126826a25fcc
      https://github.com/llvm/llvm-project/commit/3f919dfe0de84b9ec288d6126eb8126826a25fcc
  Author: Jun Ma <JunMa at linux.alibaba.com>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  Log Message:
  -----------
  [AArch64][SVE] Use getPTrue uniformly.NFC.


  Commit: 8c471034919702d83c59759bbf4c3a606ac1fab4
      https://github.com/llvm/llvm-project/commit/8c471034919702d83c59759bbf4c3a606ac1fab4
  Author: Jun Ma <JunMa at linux.alibaba.com>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
    M llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

  Log Message:
  -----------
  [AArch64][SVE] Add API for conversion between SVE predicate pattern and element number. NFC

This patch solely moves convert operation between SVE predicate pattern
and element number into two small functions. It's pre-commit patch for optimize
pture with known sve register width.

Differential Revision: https://reviews.llvm.org/D108705


  Commit: 15b2a8e7faf6b10c1371d0283a0287cf2c93ed0e
      https://github.com/llvm/llvm-project/commit/15b2a8e7faf6b10c1371d0283a0287cf2c93ed0e
  Author: Jun Ma <JunMa at linux.alibaba.com>
  Date:   2021-08-27 (Fri, 27 Aug 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
    M llvm/test/CodeGen/AArch64/sve-extract-vector.ll
    A llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

  Log Message:
  -----------
  [AArch64][SVE] Optimize ptrue predicate pattern with known sve register width.

For vectors that are exactly equal to getMaxSVEVectorSizeInBits, just use
AArch64SVEPredPattern::all, which can enable the use of unpredicated ptrue when available.

TestPlan: check-llvm

Differential Revision: https://reviews.llvm.org/D108706


Compare: https://github.com/llvm/llvm-project/compare/0dc5dc6531de...15b2a8e7faf6