[all-commits] [llvm/llvm-project] 5f848b: [X86][SchedModel] Fix latency the Hi register writ...

[Andrea Di Biagio via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5f848b311f16230479f5f991683959e45856b3f5
      https://github.com/llvm/llvm-project/commit/5f848b311f16230479f5f991683959e45856b3f5
  Author: Andrea Di Biagio <andrea.dibiagio at sony.com>
  Date:   2021-08-25 (Wed, 25 Aug 2021)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrArithmetic.td
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/lib/Target/X86/X86SchedSandyBridge.td
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/lib/Target/X86/X86Schedule.td
    M llvm/lib/Target/X86/X86ScheduleAtom.td
    M llvm/lib/Target/X86/X86ScheduleBdVer2.td
    M llvm/lib/Target/X86/X86ScheduleBtVer2.td
    M llvm/lib/Target/X86/X86ScheduleSLM.td
    M llvm/lib/Target/X86/X86ScheduleZnver1.td
    M llvm/lib/Target/X86/X86ScheduleZnver2.td
    M llvm/lib/Target/X86/X86ScheduleZnver3.td
    M llvm/test/tools/llvm-mca/X86/Haswell/mulx-hi-read-advance.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/mulx-hi-read-advance.s
    M llvm/test/tools/llvm-mca/X86/Znver2/mulx-hi-read-advance.s
    M llvm/test/tools/llvm-mca/X86/Znver3/mulx-hi-read-advance.s

  Log Message:
  -----------
  [X86][SchedModel] Fix latency the Hi register write of MULX (PR51495).

Before this patch, WriteIMulH reported a latency value which is correct for the
RR variant of MULX, but not for the RM variant.

This patch fixes the issue by introducing a new WriteIMulHLd, which is meant to
be used only by the RM variant of MULX.

Differential Revision: https://reviews.llvm.org/D108701