[all-commits] [llvm/llvm-project] 92c1fd: Allow rematerialization of virtual reg uses

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 92c1fd19abb15bc68b1127a26137a69e033cdb39
      https://github.com/llvm/llvm-project/commit/92c1fd19abb15bc68b1127a26137a69e033cdb39
  Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
  Date:   2021-08-24 (Tue, 24 Aug 2021)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/TargetInstrInfo.cpp
    M llvm/test/CodeGen/AMDGPU/remat-sop.mir
    M llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
    M llvm/test/CodeGen/ARM/funnel-shift-rot.ll
    M llvm/test/CodeGen/ARM/funnel-shift.ll
    M llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
    M llvm/test/CodeGen/ARM/neon-copy.ll
    M llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
    M llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
    M llvm/test/CodeGen/Mips/llvm-ir/shl.ll
    M llvm/test/CodeGen/Mips/llvm-ir/sub.ll
    M llvm/test/CodeGen/Mips/tls.ll
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll
    M llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
    M llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
    M llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv32zbp.ll
    M llvm/test/CodeGen/RISCV/rv32zbt.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
    M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
    M llvm/test/CodeGen/Thumb/dyn-stackalloc.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-disabled-in-loloops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/varying-outer-2d-reduction.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
    M llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
    M llvm/test/CodeGen/X86/addcarry.ll
    M llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
    M llvm/test/CodeGen/X86/dag-update-nodetomatch.ll
    M llvm/test/CodeGen/X86/inalloca-invoke.ll
    M llvm/test/CodeGen/X86/licm-regpressure.ll
    M llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
    M llvm/test/CodeGen/X86/sdiv_fix.ll

  Log Message:
  -----------
  Allow rematerialization of virtual reg uses

Currently isReallyTriviallyReMaterializableGeneric() implementation
prevents rematerialization on any virtual register use on the grounds
that is not a trivial rematerialization and that we do not want to
extend liveranges.

It appears that LRE logic does not attempt to extend a liverange of
a source register for rematerialization so that is not an issue.
That is checked in the LiveRangeEdit::allUsesAvailableAt().

The only non-trivial aspect of it is accounting for tied-defs which
normally represent a read-modify-write operation and not rematerializable.

The test for a tied-def situation already exists in the
/CodeGen/AMDGPU/remat-vop.mir,
test_no_remat_v_cvt_f32_i32_sdwa_dst_unused_preserve.

The change has affected ARM/Thumb, Mips, RISCV, and x86. For the targets
where I more or less understand the asm it seems to reduce spilling
(as expected) or be neutral. However, it needs a review by all targets'
specialists.

Differential Revision: https://reviews.llvm.org/D106408