[all-commits] [llvm/llvm-project] 194b08: [DAG] LoadedSlice::canMergeExpensiveCrossRegisterB...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 194b08000c1c3dee322acfac9fd83e055f6bc557
      https://github.com/llvm/llvm-project/commit/194b08000c1c3dee322acfac9fd83e055f6bc557
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2021-08-24 (Tue, 24 Aug 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/load-partial.ll

  Log Message:
  -----------
  [DAG] LoadedSlice::canMergeExpensiveCrossRegisterBankCopy - replace getABITypeAlign with allowsMemoryAccess (PR45116)

One of the cases identified in PR45116 - we don't need to limit load combines to ABI alignment, we can use allowsMemoryAccess - which tests using getABITypeAlign, but also checks if a target permits (fast) misaligned memory loads by checking allowsMisalignedMemoryAccesses as a fallback.