[all-commits] [llvm/llvm-project] bed587: [AggressiveInstCombine] Add arithmetic shift right...

[Anton Afanasyev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bed587631f9051f879b0672e52a58b9e8b8faab9
      https://github.com/llvm/llvm-project/commit/bed587631f9051f879b0672e52a58b9e8b8faab9
  Author: Anton Afanasyev <anton.a.afanasyev at gmail.com>
  Date:   2021-08-24 (Tue, 24 Aug 2021)

  Changed paths:
    M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
    M llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll

  Log Message:
  -----------
  [AggressiveInstCombine] Add arithmetic shift right instr to `TruncInstCombine` DAG

Add `ashr` instruction to the DAG post-dominated by `trunc`, allowing
`TruncInstCombine` to reduce bitwidth of expressions containing
these instructions.

We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are sign bits (all zeros or ones) and
one sign bit is left untruncated: https://alive2.llvm.org/ce/z/Ajo2__

Part of https://reviews.llvm.org/D107766

Differential Revision: https://reviews.llvm.org/D108355