[all-commits] [llvm/llvm-project] 955c94: [AArch64] Add Scheduling tests for Load/Store Read...

David Green via All-commits all-commits at lists.llvm.org
Mon Aug 23 13:08:11 PDT 2021


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 955c9437fd605216445fbd608de4ef1d96f825e9
      https://github.com/llvm/llvm-project/commit/955c9437fd605216445fbd608de4ef1d96f825e9
  Author: David Green <david.green at arm.com>
  Date:   2021-08-23 (Mon, 23 Aug 2021)

  Changed paths:
    A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-readadv.s
    A llvm/test/tools/llvm-mca/AArch64/Cortex/A55-store-readadv.s

  Log Message:
  -----------
  [AArch64] Add Scheduling tests for Load/Store ReadAdv operands.


  Commit: 50f4ae58eb136bc9d802cb98f02b6ff237eb61e0
      https://github.com/llvm/llvm-project/commit/50f4ae58eb136bc9d802cb98f02b6ff237eb61e0
  Author: David Green <david.green at arm.com>
  Date:   2021-08-23 (Mon, 23 Aug 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrFormats.td
    M llvm/lib/Target/AArch64/AArch64SchedA53.td
    M llvm/lib/Target/AArch64/AArch64SchedA55.td
    M llvm/lib/Target/AArch64/AArch64SchedA57.td
    M llvm/lib/Target/AArch64/AArch64SchedA64FX.td
    M llvm/lib/Target/AArch64/AArch64SchedCyclone.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedFalkor.td
    M llvm/lib/Target/AArch64/AArch64SchedKryo.td
    M llvm/lib/Target/AArch64/AArch64SchedTSV110.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
    M llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
    M llvm/lib/Target/AArch64/AArch64Schedule.td
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-store-readadv.s

  Log Message:
  -----------
  [AArch64] Correct store ReadAdrBase operand

It appears that the Read operand for stores was being placed on the
first operand (the stored value) not the address base. This adds a
ReadST for the stored value operand, allowing the ReadAdrBase to
correctly act upon the address.

Differential Revision: https://reviews.llvm.org/D108287


Compare: https://github.com/llvm/llvm-project/compare/4aeeb91a9249...50f4ae58eb13


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