[all-commits] [llvm/llvm-project] a0051f: [AArch64][GlobalISel] Fix miscompile of <16 x s8> ...

[Amara Emerson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a0051f71499bbe92fd15e9fb25005e7c55f6e9bd
      https://github.com/llvm/llvm-project/commit/a0051f71499bbe92fd15e9fb25005e7c55f6e9bd
  Author: Amara Emerson <amara at apple.com>
  Date:   2021-08-19 (Thu, 19 Aug 2021)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Fix miscompile of <16 x s8> G_EXTRACT_VECTOR_ELT.

When support for copying vector s8 lanes was added recently, this also
had the side effect of fixing a fallback for <16 x s8> extracts since
both used the same helper. However, there was a bug in another helper
to get the regclass for a specific FPR-native type, which was assigning
FPR16 to s8 instead of FPR8.