[all-commits] [llvm/llvm-project] b311a0: [WebAssembly] Pattern match SIMD convert_low and p...

[Thomas Lively via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b311a040ef9cda6d52fdfdd4968f2dc59ccf596e
      https://github.com/llvm/llvm-project/commit/b311a040ef9cda6d52fdfdd4968f2dc59ccf596e
  Author: Thomas Lively <tlively at google.com>
  Date:   2021-08-19 (Thu, 19 Aug 2021)

  Changed paths:
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/test/CodeGen/WebAssembly/simd-conversions.ll

  Log Message:
  -----------
  [WebAssembly] Pattern match SIMD convert_low and promote_low during ISel

Since the simplest DAG patterns for convert_low and promote_low instructions
involved v2i32, v2f32, v4i64, and v4f64 types, which are not legal in the
WebAssembly backend and would be eliminated by type legalization, we were
previously matching those patterns in a DAG combine before the type legalization
stage. However in cases where the vectors were wider than 128 bits, the patterns
we matched were not created until the type legalization stage when the wide
vectors were split up. Type legalization would continue to eliminate the illegal
types we were matching as well, so the code ended up scalarized.

To make the ISel for these instructions more robust, match the scalarized
patterns rather than the patterns containing illegal types. Add tests with
double-wide vectors to show that this works as intended.

Fixes PR51098.
Depends on D107502.

Differential Revision: https://reviews.llvm.org/D108266