[all-commits] [llvm/llvm-project] b69374: [WebAssembly] Legalize vector types by widening

[Thomas Lively via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b69374ca58d3e5e62688efd8149417499096d8a7
      https://github.com/llvm/llvm-project/commit/b69374ca58d3e5e62688efd8149417499096d8a7
  Author: Thomas Lively <tlively at google.com>
  Date:   2021-08-19 (Thu, 19 Aug 2021)

  Changed paths:
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
    M llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
    M llvm/test/CodeGen/WebAssembly/simd-concat.ll
    M llvm/test/CodeGen/WebAssembly/simd-extending.ll
    M llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
    R llvm/test/CodeGen/WebAssembly/simd-nonconst-sext.ll
    M llvm/test/CodeGen/WebAssembly/simd-offset.ll
    R llvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll

  Log Message:
  -----------
  [WebAssembly] Legalize vector types by widening

The default legalization of unsupported vector types is to promote the integers
in each lane, which leads to extra sign or zero extending and masking when
moving data into and out of vectors. Switch our preferred type legalization from
the default to vector widening, which keeps the data in the low lanes of the
vector rather than in the low bits of each lane. The unused high lanes can be
ignored.

Half-wide vectors are now loaded from memory into the low 64 bits of the v128
rather than spread out among the lanes. As a result, v128.load64_splat is a much
more common operation, so add new patterns to support it.

Differential Revision: https://reviews.llvm.org/D107502