[all-commits] [llvm/llvm-project] d10f23: [ISel] Expand saddsat and ssubsat via asr and xor

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d10f23a25d5c7b6dd61cbab8e16bf2099151be42
      https://github.com/llvm/llvm-project/commit/d10f23a25d5c7b6dd61cbab8e16bf2099151be42
  Author: David Green <david.green at arm.com>
  Date:   2021-08-19 (Thu, 19 Aug 2021)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sadd_sat.ll
    M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
    M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/ssub_sat.ll
    M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
    M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
    M llvm/test/CodeGen/AMDGPU/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/ssubsat.ll
    M llvm/test/CodeGen/ARM/qdadd.ll
    M llvm/test/CodeGen/ARM/sadd_sat.ll
    M llvm/test/CodeGen/ARM/sadd_sat_plus.ll
    M llvm/test/CodeGen/ARM/ssub_sat.ll
    M llvm/test/CodeGen/ARM/ssub_sat_plus.ll
    M llvm/test/CodeGen/PowerPC/sat-add.ll
    M llvm/test/CodeGen/RISCV/sadd_sat.ll
    M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
    M llvm/test/CodeGen/RISCV/ssub_sat.ll
    M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
    M llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
    M llvm/test/CodeGen/X86/combine-add-ssat.ll
    M llvm/test/CodeGen/X86/sadd_sat.ll
    M llvm/test/CodeGen/X86/sadd_sat_plus.ll
    M llvm/test/CodeGen/X86/sadd_sat_vec.ll
    M llvm/test/CodeGen/X86/ssub_sat.ll
    M llvm/test/CodeGen/X86/ssub_sat_plus.ll
    M llvm/test/CodeGen/X86/ssub_sat_vec.ll

  Log Message:
  -----------
  [ISel] Expand saddsat and ssubsat via asr and xor

This changes the lowering of saddsat and ssubsat so that instead of
using:
  r,o = saddo x, y
  c = setcc r < 0
  s = c ? INTMAX : INTMIN
  ret o ? s : r
into using asr and xor to materialize the INTMAX/INTMIN constants:
  r,o = saddo x, y
  s = ashr r, BW-1
  x = xor s, INTMIN
  ret o ? x : r
https://alive2.llvm.org/ce/z/TYufgD

This seems to reduce the instruction count in most testcases across most
architectures. X86 has some custom lowering added to compensate for
cases where it can increase instruction count.

Differential Revision: https://reviews.llvm.org/D105853