[all-commits] [llvm/llvm-project] 2498c3: [Test][AggressiveInstCombine] Add one more tests f...

[Anton Afanasyev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2498c3edcdd271905851d69346be6d24ed292999
      https://github.com/llvm/llvm-project/commit/2498c3edcdd271905851d69346be6d24ed292999
  Author: Anton Afanasyev <anton.a.afanasyev at gmail.com>
  Date:   2021-08-18 (Wed, 18 Aug 2021)

  Changed paths:
    M llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll

  Log Message:
  -----------
  [Test][AggressiveInstCombine] Add one more tests for shifts


  Commit: cfb6dfcbd13b417f83d8adca69b60ba4254b4233
      https://github.com/llvm/llvm-project/commit/cfb6dfcbd13b417f83d8adca69b60ba4254b4233
  Author: Anton Afanasyev <anton.a.afanasyev at gmail.com>
  Date:   2021-08-18 (Wed, 18 Aug 2021)

  Changed paths:
    M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
    M llvm/test/Transforms/AggressiveInstCombine/pr50555.ll
    M llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
    M llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll

  Log Message:
  -----------
  [AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG

Add `lshr` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions containing
these instructions.

We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are zeros: https://alive2.llvm.org/ce/z/_LytbB

Alive2 variable-length proof:
https://godbolt.org/z/1srE1aqzf => s/32/8/ => https://alive2.llvm.org/ce/z/StwPia

Part of https://reviews.llvm.org/D107766

Differential Revision: https://reviews.llvm.org/D108201


Compare: https://github.com/llvm/llvm-project/compare/76c971219690...cfb6dfcbd13b