[all-commits] [llvm/llvm-project] 237994: [X86] AVX512FP16 instructions enabling 3/6

[Pengfei Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2379949aadcee8d4028dec0508f88bda290636bc
      https://github.com/llvm/llvm-project/commit/2379949aadcee8d4028dec0508f88bda290636bc
  Author: Wang, Pengfei <pengfei.wang at intel.com>
  Date:   2021-08-18 (Wed, 18 Aug 2021)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsX86.def
    M clang/include/clang/Basic/BuiltinsX86_64.def
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Headers/avx512fp16intrin.h
    M clang/lib/Headers/avx512vlfp16intrin.h
    M clang/lib/Sema/SemaChecking.cpp
    M clang/test/CodeGen/X86/avx512fp16-builtins.c
    M clang/test/CodeGen/X86/avx512vlfp16-builtins.c
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/include/llvm/IR/RuntimeLibcalls.def
    M llvm/lib/CodeGen/TargetLoweringBase.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrFoldTables.cpp
    M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrSSE.td
    M llvm/lib/Target/X86/X86IntrinsicsInfo.h
    M llvm/test/CodeGen/X86/avx512fp16-arith-intrinsics.ll
    M llvm/test/CodeGen/X86/avx512fp16-arith-vl-intrinsics.ll
    M llvm/test/CodeGen/X86/avx512fp16-arith.ll
    A llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-intrinsics.ll
    A llvm/test/CodeGen/X86/avx512fp16-cvt-ph-w-vl-intrinsics.ll
    A llvm/test/CodeGen/X86/avx512fp16-cvt.ll
    M llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
    M llvm/test/CodeGen/X86/avx512fp16vl-intrinsics.ll
    A llvm/test/CodeGen/X86/cvt16-2.ll
    M llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll
    A llvm/test/CodeGen/X86/fp-strict-scalar-fptoint-fp16.ll
    A llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll
    M llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll
    M llvm/test/CodeGen/X86/vec-strict-128-fp16.ll
    M llvm/test/CodeGen/X86/vec-strict-256-fp16.ll
    M llvm/test/CodeGen/X86/vec-strict-512-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-fptoint-128-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-fptoint-256-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-fptoint-512-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-inttofp-128-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-inttofp-256-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-inttofp-512-fp16.ll
    M llvm/test/MC/Disassembler/X86/avx512fp16.txt
    M llvm/test/MC/Disassembler/X86/avx512fp16vl.txt
    M llvm/test/MC/X86/avx512fp16.s
    M llvm/test/MC/X86/avx512fp16vl.s
    M llvm/test/MC/X86/intel-syntax-avx512fp16.s
    M llvm/test/MC/X86/intel-syntax-avx512fp16vl.s

  Log Message:
  -----------
  [X86] AVX512FP16 instructions enabling 3/6

Enable FP16 conversion instructions.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105265