[all-commits] [llvm/llvm-project] 1f3e35: [AggressiveInstCombine] Add shift left instruction...

[Anton Afanasyev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1f3e35b6d165715ec7bf7ba80d5b982719c7752a
      https://github.com/llvm/llvm-project/commit/1f3e35b6d165715ec7bf7ba80d5b982719c7752a
  Author: Anton Afanasyev <anton.a.afanasyev at gmail.com>
  Date:   2021-08-17 (Tue, 17 Aug 2021)

  Changed paths:
    M llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
    M llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll

  Log Message:
  -----------
  [AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG

Add `shl` instruction to the DAG post-dominated by `trunc`, allowing
TruncInstCombine to reduce bitwidth of expressions containing left shifts.

The only thing we need to check is that the target bitwidth must be wider
than the maximal shift amount: https://alive2.llvm.org/ce/z/AwArqu

Part of https://reviews.llvm.org/D107766

Differential Revision: https://reviews.llvm.org/D108091