[all-commits] [llvm/llvm-project] f1de9d: [X86] AVX512FP16 instructions enabling 2/6

[Pengfei Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f1de9d6dae174feb5000ad6a1b492b8cb717f5b6
      https://github.com/llvm/llvm-project/commit/f1de9d6dae174feb5000ad6a1b492b8cb717f5b6
  Author: Wang, Pengfei <pengfei.wang at intel.com>
  Date:   2021-08-15 (Sun, 15 Aug 2021)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsX86.def
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/Headers/avx512fp16intrin.h
    M clang/lib/Headers/avx512vlfp16intrin.h
    M clang/lib/Sema/SemaChecking.cpp
    M clang/test/CodeGen/X86/avx512fp16-builtins.c
    M clang/test/CodeGen/X86/avx512vlfp16-builtins.c
    M llvm/include/llvm/IR/IntrinsicsX86.td
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrFoldTables.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86IntrinsicsInfo.h
    A llvm/test/CodeGen/X86/avx512fp16-arith-intrinsics.ll
    A llvm/test/CodeGen/X86/avx512fp16-arith-vl-intrinsics.ll
    A llvm/test/CodeGen/X86/avx512fp16-arith.ll
    A llvm/test/CodeGen/X86/avx512fp16-fmaxnum.ll
    A llvm/test/CodeGen/X86/avx512fp16-fminnum.ll
    A llvm/test/CodeGen/X86/avx512fp16-fold-load-binops.ll
    A llvm/test/CodeGen/X86/avx512fp16-fold-xmm-zero.ll
    A llvm/test/CodeGen/X86/avx512fp16-fp-logic.ll
    A llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
    A llvm/test/CodeGen/X86/avx512fp16-machine-combiner.ll
    M llvm/test/CodeGen/X86/avx512fp16-mov.ll
    A llvm/test/CodeGen/X86/avx512fp16-unsafe-fp-math.ll
    A llvm/test/CodeGen/X86/fp-strict-scalar-cmp-fp16.ll
    A llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll
    M llvm/test/CodeGen/X86/pseudo_cmov_lower-fp16.ll
    A llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll
    A llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll
    A llvm/test/CodeGen/X86/vec-strict-128-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-256-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-512-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-cmp-128-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-cmp-256-fp16.ll
    A llvm/test/CodeGen/X86/vec-strict-cmp-512-fp16.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmax-nnan.ll
    M llvm/test/CodeGen/X86/vector-reduce-fmin-nnan.ll
    M llvm/test/MC/Disassembler/X86/avx512fp16.txt
    A llvm/test/MC/Disassembler/X86/avx512fp16vl.txt
    M llvm/test/MC/X86/avx512fp16.s
    A llvm/test/MC/X86/avx512fp16vl.s
    M llvm/test/MC/X86/intel-syntax-avx512fp16.s
    A llvm/test/MC/X86/intel-syntax-avx512fp16vl.s

  Log Message:
  -----------
  [X86] AVX512FP16 instructions enabling 2/6

Enable FP16 binary operator instructions.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105264