[all-commits] [llvm/llvm-project] e25665: [RISCV] Add test cases showing inefficient materia...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e25665f52eff4f99153c881df31b77824af430fe
      https://github.com/llvm/llvm-project/commit/e25665f52eff4f99153c881df31b77824af430fe
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-12 (Thu, 12 Aug 2021)

  Changed paths:
    M llvm/test/CodeGen/RISCV/imm.ll

  Log Message:
  -----------
  [RISCV] Add test cases showing inefficient materialization for stores of immediates. NFC

DAGCombiner::visitStore can call GetDemandedBits which will remove
upper bits from immediates. The upper bits are important for good
materialization of negative constants on RISCV. GetDemandedBits is a
different mechanism than SimplifyDemandedBits so
TargetShrinkDemandedConstant can't block it.

As far as I know this behavior is unique to stores.

I think we can fix this in isel using a concept similar to D107658.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D107860