[all-commits] [llvm/llvm-project] 6171f8: [RISCV] Use getNaturalPointeeTypeAlignment to get ...

Craig Topper via All-commits all-commits at lists.llvm.org
Thu Aug 12 10:05:57 PDT 2021


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6171f84942ce2136b464ac0e8e620c6908f64cc6
      https://github.com/llvm/llvm-project/commit/6171f84942ce2136b464ac0e8e620c6908f64cc6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-12 (Thu, 12 Aug 2021)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td

  Log Message:
  -----------
  [RISCV] Use getNaturalPointeeTypeAlignment to get alignment for stores created for vector builtins.

Instead of using scalar size divided by 8 for segment loads, get
the alignment from clang's type system.

Make vleff match for consistency.

Also replace uses of getPointerElementType() which will be removed as part of the OpaquePtr changes.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D106738


  Commit: f66ba5fcef19ff03532d993ac4af1362a89b833f
      https://github.com/llvm/llvm-project/commit/f66ba5fcef19ff03532d993ac4af1362a89b833f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-12 (Thu, 12 Aug 2021)

  Changed paths:
    M clang/lib/Sema/SemaDeclCXX.cpp

  Log Message:
  -----------
  [Sema] Fix -Wparentheses warning from gcc. NFC


  Commit: 79fbddbea0c6940587acf5353af4557ee9524bbe
      https://github.com/llvm/llvm-project/commit/79fbddbea0c6940587acf5353af4557ee9524bbe
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2021-08-12 (Thu, 12 Aug 2021)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

  Log Message:
  -----------
  [RISCV] Teach vsetvli insertion pass that it doesn't need to insert vsetvli for unit-stride or strided loads/stores in some cases.

For unit-stride and strided load/stores we set the SEW operand of
the pseudo instruction equal the EEW in the opcode. The LMUL
of the pseudo instruction is the LMUL we want.

These instructions calculate EMUL=(EEW/SEW) * LMUL. We can use
this to avoid changing vtype if the SEW/LMUL of the previous
vtype matches the EEW/EMUL ratio we need for the instruction.

Due to how the global analysis works, we can only do this
optimization when the previous vsetvli was produced in the block
containing the store. We need to know in the first phase if the
vsetvli will be inserted so we can propagate information to
the successors in the second phase correctly. This means we can't
depend on predecessors.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D106601


Compare: https://github.com/llvm/llvm-project/compare/f30a7dff8a5b...79fbddbea0c6


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