[all-commits] [llvm/llvm-project] 79b057: [mlir] Tighten LLVM_AnyNonAggregate ODS type const...
ftynse via All-commits
all-commits at lists.llvm.org
Wed Aug 11 07:30:38 PDT 2021
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 79b0576dd477c1d6ad608486ffff6213cca32db9
https://github.com/llvm/llvm-project/commit/79b0576dd477c1d6ad608486ffff6213cca32db9
Author: Alex Zinenko <zinenko at google.com>
Date: 2021-08-11 (Wed, 11 Aug 2021)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOpBase.td
M mlir/test/Dialect/LLVMIR/invalid.mlir
Log Message:
-----------
[mlir] Tighten LLVM_AnyNonAggregate ODS type constraint
The constraint was checking that the type is not an LLVM structure or array
type, but was not checking that it is an LLVM-compatible type, making it accept
incorrect types. As a result, some LLVM dialect ops could process values that
are not compatible with the LLVM dialect leading to further issues with
conversions and translations that assume all values are LLVM-compatible. Make
LLVM_AnyNonAggregate only accept LLVM-compatible types.
Reviewed By: cota, akuegel
Differential Revision: https://reviews.llvm.org/D107889
Commit: a0d8a08e3e8b77fd1699fa7083e6d0b8548d67e1
https://github.com/llvm/llvm-project/commit/a0d8a08e3e8b77fd1699fa7083e6d0b8548d67e1
Author: Alex Zinenko <zinenko at google.com>
Date: 2021-08-11 (Wed, 11 Aug 2021)
Changed paths:
M mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
M mlir/test/Conversion/StandardToLLVM/convert-nd-vector-to-llvmir.mlir
M mlir/test/Conversion/StandardToLLVM/standard-to-llvm.mlir
Log Message:
-----------
[mlir] Add std.bitcast -> llvm.bitcast conversion
The conversion is a straightforward one-to-one mapping with optional unrolling
for nD vectors, similarly to other cast operations.
Depends On D107889
Reviewed By: cota, akuegel
Differential Revision: https://reviews.llvm.org/D107891
Compare: https://github.com/llvm/llvm-project/compare/62c08c021dbf...a0d8a08e3e8b
More information about the All-commits
mailing list