[all-commits] [llvm/llvm-project] 1b4194: RegAllocGreedy: Add spaces between registers in de...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1b41945da0c180aa5d6fb82e9fcc9cebcc4cae30
      https://github.com/llvm/llvm-project/commit/1b41945da0c180aa5d6fb82e9fcc9cebcc4cae30
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-08-10 (Tue, 10 Aug 2021)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocGreedy.cpp

  Log Message:
  -----------
  RegAllocGreedy: Add spaces between registers in debug message


  Commit: d84c4e385721ceb7fe3ef0bff88ed6a51a5337da
      https://github.com/llvm/llvm-project/commit/d84c4e385721ceb7fe3ef0bff88ed6a51a5337da
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-08-10 (Tue, 10 Aug 2021)

  Changed paths:
    A llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir

  Log Message:
  -----------
  AMDGPU: Add baseline register allocation failure test


  Commit: d719f1c3cc9c6f44438b4bd847816d7462945269
      https://github.com/llvm/llvm-project/commit/d719f1c3cc9c6f44438b4bd847816d7462945269
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2021-08-10 (Tue, 10 Aug 2021)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/ctpop16.ll
    M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
    M llvm/test/CodeGen/AMDGPU/fix-frame-ptr-reg-copy-livein.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll
    M llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
    M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
    M llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    M llvm/test/CodeGen/AMDGPU/indirect-call.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
    M llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll
    M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll

  Log Message:
  -----------
  AMDGPU: Add alloc priority to global ranges

The requested register class priorities weren't respected
globally. Not sure why this is a target option, and not just the
expected behavior (recently added in
1a6dc92be7d68611077f0fb0b723b361817c950c). This avoids an allocation
failure when many wide tuple spills are introduced. I think this is a
workaround since I would not expect the allocation priority to be
required, and only a performance hint. The allocator should be smarter
about when only a subregister needs to be spilled and restored.

This does regress a couple of degenerate store stress lit tests which
shouldn't be too important.


Compare: https://github.com/llvm/llvm-project/compare/3b39fa3e2815...d719f1c3cc9c