[all-commits] [llvm/llvm-project] 6f7f5b: [X86] AVX512FP16 instructions enabling 1/6

[Pengfei Wang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f7f5b54c81be59ec7876649d1f9aa6b104658ec
      https://github.com/llvm/llvm-project/commit/6f7f5b54c81be59ec7876649d1f9aa6b104658ec
  Author: Wang, Pengfei <pengfei.wang at intel.com>
  Date:   2021-08-10 (Tue, 10 Aug 2021)

  Changed paths:
    M clang/docs/ClangCommandLineReference.rst
    M clang/docs/LanguageExtensions.rst
    M clang/docs/ReleaseNotes.rst
    M clang/include/clang/Basic/BuiltinsX86.def
    M clang/include/clang/Driver/Options.td
    M clang/lib/Basic/Targets/X86.cpp
    M clang/lib/Basic/Targets/X86.h
    M clang/lib/CodeGen/CGBuiltin.cpp
    M clang/lib/CodeGen/TargetInfo.cpp
    M clang/lib/Headers/CMakeLists.txt
    A clang/lib/Headers/avx512fp16intrin.h
    A clang/lib/Headers/avx512vlfp16intrin.h
    M clang/lib/Headers/cpuid.h
    M clang/lib/Headers/immintrin.h
    A clang/test/CodeGen/X86/avx512fp16-abi.c
    A clang/test/CodeGen/X86/avx512fp16-builtins.c
    A clang/test/CodeGen/X86/avx512vlfp16-builtins.c
    M clang/test/CodeGen/attr-target-x86.c
    M clang/test/Driver/x86-target-features.c
    M clang/test/Preprocessor/predefined-arch-macros.c
    M clang/test/Preprocessor/x86_target_features.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
    M llvm/include/llvm/Support/X86TargetParser.def
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
    M llvm/lib/Support/Host.cpp
    M llvm/lib/Support/X86TargetParser.cpp
    M llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
    M llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
    M llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
    M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86CallingConv.td
    M llvm/lib/Target/X86/X86FastISel.cpp
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrCompiler.td
    M llvm/lib/Target/X86/X86InstrFormats.td
    M llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrInfo.td
    M llvm/lib/Target/X86/X86InstrVecCompiler.td
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/lib/Target/X86/X86Schedule.td
    M llvm/lib/Target/X86/X86Subtarget.h
    M llvm/lib/Target/X86/X86TargetTransformInfo.cpp
    A llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-broadcast-fp16.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-reverse-fp16.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-single-src-fp16.ll
    A llvm/test/Analysis/CostModel/X86/shuffle-two-src-fp16.ll
    M llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
    A llvm/test/CodeGen/X86/avx512fp16-insert-extract.ll
    A llvm/test/CodeGen/X86/avx512fp16-mov.ll
    A llvm/test/CodeGen/X86/avx512fp16-mscatter.ll
    A llvm/test/CodeGen/X86/avx512fp16-subv-broadcast-fp16.ll
    A llvm/test/CodeGen/X86/avx512fp16vl-intrinsics.ll
    M llvm/test/CodeGen/X86/fp128-cast-strict.ll
    A llvm/test/CodeGen/X86/pseudo_cmov_lower-fp16.ll
    M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
    A llvm/test/MC/Disassembler/X86/avx512fp16.txt
    A llvm/test/MC/X86/avx512fp16.s
    A llvm/test/MC/X86/intel-syntax-avx512fp16.s
    M llvm/test/MachineVerifier/test_copy_physregs_x86.mir
    M llvm/utils/TableGen/X86DisassemblerTables.cpp
    M llvm/utils/TableGen/X86DisassemblerTables.h
    M llvm/utils/TableGen/X86RecognizableInstr.cpp
    M llvm/utils/TableGen/X86RecognizableInstr.h

  Log Message:
  -----------
  [X86] AVX512FP16 instructions enabling 1/6

1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.

Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html

Reviewed By: LuoYuanke

Differential Revision: https://reviews.llvm.org/D105263